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SUB-LITHO GATE LENGTH TECHNIQUE FOR DEEP SUBĀµ CMOS/BICMOS APPLICATIONS

IP.com Disclosure Number: IPCOM000006309D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-24
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

Authors:
Bor-Yuan Hwang Margaret Huang Irfan Rahim

Abstract

This process technique described here can achieve a short gate poly length with precise control down to sub- litho geometry. Standard process steps are used to achieve this structure without applying processes beyond the pres- ent technology capability. This sub-litho gate poly length definition alIows tier improvement in MOS device per- formance by reducing Leff without sacrificing the excessive overlapping capacitance between gate to source and draii (Cgd and Cgs).