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STRUCTURE FOR REDUCED SOURCE AND DRAIN AREA BY SELECTIVE SILICON

IP.com Disclosure Number: IPCOM000006321D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-25

Publishing Venue

Motorola

Related People

Authors:
Jon Fitch Carlos Mazurk Dean Denning Jim Pfiester

Abstract

The spacing between adjacent gate lines in submicron technology is limited by the minimum isolation spacing and by the minimum source and drain window size necessary to form a contact. If one could reduce the source and drain window size then, for the same isola- tion spacing, one could realize (1) an improvement in device packing density and (2) a reduction in S/D junction capacitance.