HIGH SELECTIVITY CONTACT ETCH FOR BiCMOS AND CMOS
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-25
As circuit features have been reduced to the l/./m range, the difficulty of opening contacts has increased significantly, While there are several important aspects to a successful contact etch, the ability to completely clear. oxide (or other dielectric) from the window without removal of the underlying substrate is perhaps the most critical. The margin between overetch (which can create shorted or leaky junctions) and underetch (which results in high resistance or opens) is narrowed because VLSI devices require shallow junctions while advanced multilayer metal systems require planarization of the thick (0.5-1.0 pm) dielectric (ILDO) underneath first metal. A planarized ILDO provides process margin for metal patterning and electromigration resistance, but creates varying oxide thicknesses (tax) over the individual contacts. Since the difference in tax can be ~0.4 pm, a high selectivity etch (oxide to silicon) to minimize etching of the shallow junctions (~0.2 pm) is required.