Browse Prior Art Database

METHOD FOR SENSOR SUBSTRATE BIAS

IP.com Disclosure Number: IPCOM000006351D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-27

Publishing Venue

Motorola

Related People

Authors:
Ira Baskett

Abstract

The substrate can be biased positive with respect to the P+ interconnects by an alternate method. By mak- ing contact to the small P+ diffusion area with the power supply metal and damaging this P+ to substrate junc- tion by suffGent reverse bias voltage, a low resistance path is formed to allow current to flow (see Figure 1). This starves the parasitic PNP of base current and decreases the back-gate bias of the parasitic MOSFET This technique is similar to the Zener diode zap trim method used in the manufacture of operational amplfi- ers. Further advantage can be gained by applying laser heat during the junction damaging or shorting process. The use of a lower current and voltage level will help to ensure that no other component on the chip is damaged or that no other voltage breakdown will occur, and that maximum productivity can be maintained. Implementing this junction-damage process at water probe will be most cost efficient.