Browse Prior Art Database

METHOD FOR WET ETCH OF EMITTER CONTACT FOR CMOS BASED DOUBLE POLY BiCMOS PROCESS

IP.com Disclosure Number: IPCOM000006361D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2001-Dec-28
Document File: 2 page(s) / 86K

Publishing Venue

Motorola

Related People

Authors:
Robert H. Reuss Terry S. Hulseweh

Abstract

In BiCMOS flows based on SRAM products, the NPN (Figure 1) is usually fabricated after the CMOS implants and deposition of the interpoly LTO (2-3KA) by etching an emitter contact to the active base region and then deposition of a second poly layer to serve as both emitter and load resistor! A problem with this proc- ess is that the emitter contact must be opened by RIE in order to maintain dimensional control (wet etch would give larger and variable emitter area). The RIE process requires compromises, however, because of the follow- ing trade-offs: 1. Residual oxide in the emitter window (underetch) results in catastrophic emitter resistance and poor or no emitter base junction formation.