PERIPHERAL ERROR CALCULATOR
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-01
In a pager with a microcomputer based decoder, this invention will allow a microprocessor to run at a lower bus rate when doing address correlations. During the process of address correlation, the current micro- processors require a substantial amount of ROM and/or CPU cycles to calculate the weight (number of l's) in a byte. They must either use a serial shift process and add method, or use a large look-up table method. The cycle time of correlating is particularly critical in early address shut down type battery saving. For example, the aver- age current drain increases by 1 A for every 200 micro- seconds of CPU timing used up in the correlation process using a typical paging protocol.