PIPELINED SYNCHRONOUS MEMORY ACCESS
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-03
Single ported synchronous memories usually have a single address access path referenced to a given clock edge. Memory applications with multiple address sources must arbitrate between these sources for access to the single port. Adding additional ports to a memory array may exceed the allowable chip area or complexity. Oper- ating the memory at twice the speed of the external clock is not possible for large memory arrays operating in fast environments. An example of a memory application using multiple address paths is a multiprocessing cache tag which must service processor, snoop, and flush requests. This paper describes a method for "pipelining" the accesses to a single port tag memory for better utiliza- tion of the memory array bandwidth.