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A Packet Formatting Mechanism for RapidIO Disclosure Number: IPCOM000006507D
Original Publication Date: 2002-Jan-11
Included in the Prior Art Database: 2002-Jan-11

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Srinath Audityan Jose M Nunez


This paper discloses a packet formatting mechanism that is area efficient and has minimal logic implementation complexity. The important components of the circuit are: a packet based bus architecture and packet formatting logic to convert internal bus transactions to packet transactions.