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A Double-Data-Rate (DDR) Transmit Structure Disclosure Number: IPCOM000006511D
Original Publication Date: 2002-Jan-11
Included in the Prior Art Database: 2002-Jan-11

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Srinath Audityan Jose M Nunez


This paper describes a DDR (double data-rate) transmit mechanism that does not require a dedicated PLL (phase locked loop) circuit. The important components of the proposal are: DDR interface, and a transmit structure to generate DDR data on the interface. This circuit eliminates the need for a dedicated PLL for implementing a DDR transmit structure using a 1X clock. This simplifies chip integration tasks and reduces the area usage of a DDR transmit structure