HIGH-PERFORMANCE SELF-ALIGNED NPN FOR BICMOS
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2002-Jan-14
There are a number of methods for fabrication of bipolar transistors within a BiCMOS process. In gen- eral, a CMOS baseline process with only a few added steps to form the bipolar transistor is a preferred approach because of simplicity and compatibility with existing process technology. The emitter-base structure of an NPN device can easily be formed by adding a non-critical, base-implant mask, an emitter-contact mask, and an arsenic-doped-polysilicon emitter layer to a CMOS base- line process. A relatively small amount of incremental process complexity provides a modest performance NPN that significantly adds to the capability of the original CMOS flow. While this procedure for integration of an NPN has been successfully demonstrated (1,2), there are several problems with this method that can result in yield and/or performance limitations. A method to over- come these limitations without losing the overall sim- plicity and ease of integration into CMOS is desirable.