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Disclosed is a method for high-density routing and interconnection for flip chip packaging. Benefits include higher density signal trace routing on the package substrate and reduced die size.
English (United States)
This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately
50% of the total text.
Method for high-density routing and interconnection for
flip chip packaging
Disclosed is a method for high-density routing and
interconnection for flip chip packaging. Benefits include higher density signal
trace routing on the package substrate and reduced die size.
disclosed method consists of a means for implementing high-density
interconnection and routing of flip chip die to package interconnections.
flip chip packaging, such as OLGA and FC-BGA utilize solder bumps arranged in a
regular array, as shown in Figure 1, to connect the silicon die to the
package. Routing of this type of array has been limited due to the placement
and diameter of the bumps. These limitations effectively reduce the
interconnection density of the die-to-package interconnect, translating into
larger silicon die for I/O ring limited products. For example, the effective
trace pitch, per substrate route layer of the method illustrated in
Figure 1 is 160 microns, assuming standard FC-BGA design rules.
disclosed method optimizes the placement of the bumps to enable higher density
routing of signal traces on the package substrate by minimizing the effect of
the solder bump diameter.
location of the bumps can be subordinated to the route capabilities of the
substrate. In this case, the bumps can be placed so that the traces routing to
them are located at a minimum pitch corresponding to the line width and spacing
of the traces on the substrate, as shown in Figure 2. For example, where the trace
width and space i...