Browse Prior Art Database

MULTI-PILLAR SURROUNDING GATE TRANSISTOR WITH ADVANCED ISOLATION

IP.com Disclosure Number: IPCOM000006677D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-23
Document File: 5 page(s) / 232K

Publishing Venue

Motorola

Related People

Authors:
Jon Fitch Carlos Mazure

Abstract

The conventional planar MOSFET with LOCOS type isolation suffers from two problems with respect to scalability: (1) the scalability of the MOSFET is limited by short channel effects and by the minimum resolva- ble feature size of present day photolithography tools, and (2) lateral encroachment into the active area is a limiting factor for LOCOS and LOCOS-lie isolation schemes, and (3) the device density on an IC is limited by the minimum area required to construct a MOSFET which is roughly 10 times the square of the minimum feature size, i.e. lOF2. Thus, the scalability of the con- ventional MOSFET is limited and the down sizing of device dimensions may not be enough to meet future scaling requirements.