Browse Prior Art Database

UNDERGATED TFTS WITH P + POLY/TiN GATES

IP.com Disclosure Number: IPCOM000006678D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-23
Document File: 2 page(s) / 105K

Publishing Venue

Motorola

Related People

Authors:
Frank K. Baker Thomas McNelly A. R. Sitaram BichYen Nguyen

Abstract

Static RAMS with densities of 16Mb or more will require polysilicon PMOS thin-film transistor (TFT) loads in order to control standby current, improve the soft error rate, overcome diode leakage problems, and allow supply voltage scaling. The most ,common implementa- tion of the TFT load involves forming a pair of polysilicon gate electrodes, which attach to the SRAM data storage nodes, and then forming polysilicon channels which run across the top of each gate electrode, separated from the underlying gates by only a thin TFT dielectric. This is known as the "undergated" approach to TFT fabrica- tion. The technique described below utilizes TiN and p+ doped polysilicon to form the TFT gate electrodes. This choice of materials provides optimum intercon- nection between the various portions of the TFT load devices, without compromising the quality of the TFf dielectric.