Browse Prior Art Database

Mechanism to Optimize DMA Read & Write Transfers

IP.com Disclosure Number: IPCOM000006693D
Original Publication Date: 2002-Jan-23
Included in the Prior Art Database: 2002-Jan-23
Document File: 2 page(s) / 42K

Publishing Venue

Motorola

Related People

Authors:
Srinath Audityan Jose M Nunez Marie J Sullivan

Abstract

This proposes a method and apparatus for optimizing direct memory access (DMA) read papers & write transfers of different sizes to maximize system buffer utilization thereby improving the DMA performance. The important components of this idea are: a system having interfaces with different size and alignment requirements, a DMA controller that has separate source and destination controls to transfer data among all interfaces, a hardware managed static buffer allocation scheme to simplify the buffer management control logic, and a buffer pool that is shared by read & write transfers of all DMA channels.