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A Data Transfer Broadcast Mechanism Disclosure Number: IPCOM000006694D
Original Publication Date: 2002-Jan-23
Included in the Prior Art Database: 2002-Jan-23
Document File: 1 page(s) / 44K

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Srinath Audityan: AUTHOR [+1]


This proposes a method and apparatus for DMA transfer broadcast across multiple interfaces and multiple paper address ranges to improve DMA performance for graphics applications like image processing. The important components of this idea are: a system having multiple interfaces partitioned across different address ranges, a DMA controller to transfer data among all interfaces and an application like graphics which requires good data broadcast performance

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN"><DIV> A </DIV><DIV></DIV><DIV></DIV><DIV>Double-Data-Rate (DDR) Transmit Structure</DIV><DIV>

</DIV><DIV>Srinath Audityan & Jose M Nunez



</DIV><DIV></DIV><DIV>This paper describes a DDR (double data-rate) transmit mechanism that does not require a dedicated PLL (phase locked loop) circuit. </DIV><DIV>The important components of the proposal are:  DDR interface,  and a transmit structure to generate DDR data on the interface. This circuit eliminates the need for a dedicated PLL for implementing a DDR transmit structure using a 1X clock. This simplifies chip integration tasks and reduces the area usage of a DDR transmit structure.


DDR interfaces require data to be transmitted and received on each phase of a clock. DDR designs have always used a dedicated PLL to generate 2X transmit clock frequency to implement the DDR transmit structure. This circuit uses the transmit clock itself to select the data to be driven for each phase of the transmit clock.