Browse Prior Art Database

A Programmable RapidIO Data Queue Mechanism for Latency and Performance

IP.com Disclosure Number: IPCOM000006695D
Original Publication Date: 2002-Jan-23
Included in the Prior Art Database: 2002-Jan-23
Document File: 2 page(s) / 28K

Publishing Venue

Motorola

Related People

Authors:
Gus Ikonomopoulos Srinath Audityan Jose Nunez

Abstract

RapidIO requires the following ordering requirements ... 1. Packets arrive with sequential ackids (3-bit field) in increasing order, wrapping back to 0 on overflow. A packet shall only be accepted by the receiving processing element in the sequential order specified by the ackid by returning a packet-accepted control symbol. If a packet cannot be accepted, then a packet-retry control symbol is returned and all following packets are silently discarded until a restart-from-retry control symbol is received. 2. Packets that arrive within the same priority level must be strongly ordered amongst themselves. 3. As of RapidIO v1.1, four priority levels exist: 0 (lowest), 1, 2, and 3 (highest). Packets of higher priority may be allowed to bypass packets of lower priority. A data queue mechanism must satisfy all of the above ordering requirements for multiple outstanding un-acknowledged packets and maintain a high level of performance without the requirement of dedicated resources for each priority.