Browse Prior Art Database

SONOS Flash EEPROM Enhanced Programming Scheme Using a Si1-xGex Layer

IP.com Disclosure Number: IPCOM000006698D
Original Publication Date: 2002-Jan-23
Included in the Prior Art Database: 2002-Jan-23

Publishing Venue

Motorola

Related People

Authors:
Chi-Nan Brian Li

Abstract

The programming of floating gate based Non-Volatile Memory (NVM) cells using Hot Carrier Injection (HCI) programming has been main stream in the semiconductor industry for the last decade. The problem with scalability of the tunnel oxide has limited the operating voltages in flash bitcell programming. Off state column leakage in a selected column during HCI programming has also limited device scaling due to short channel effects. Recently, a back biased programming scheme has been proposed for the next generation flash (electrically erasable programmable read only memory) EEPROM programming, reducing the column leakage by increasing the effective bitcell threshold voltage, which in turn reduce the column leakage during programming.[1] At the same time, simulation work has shown that the Si1-xGex/Si substrate can increase the back-bias programming efficiency. [2] In this disclosure, a flash EEPROM NVM bitcell using (oxide-nitride-oxide) ONO as the charge storage region on a Si/Si1-xGex substrate using back bias programming scheme is proposed.