Browse Prior Art Database

AN OTP EPROM BUILT WITH A 1T FLASH EEPROM CORE

IP.com Disclosure Number: IPCOM000006713D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-24
Document File: 2 page(s) / 133K

Publishing Venue

Motorola

Related People

Authors:
Ko-Min Chang Shih K. Cheng Clinton Kuo

Abstract

Microcontrollers (MC&) thrive on the ability to be integrated with an assortment of non-volatile memories (NVMs). Typically, a large array of read-only memory (ROM) is needed for control code storage and a small array of full-featured electrically-erasable programmable ROM (EEPROM) is used for frequently-updated data storage. Due to its long torn-around time, ROMs are usually being emulated by the low-cost one-time programmable (OTP) electrically progmmmable ROMs (EPROMs). While OTP EPROMs require devices that can handle - 12V, full-featured EEPROMs require dif- ferent devices that can handle -20V and a high quality thin tunnel oxide. Although the availabiity of an assort- ment of NVMs on one chip is highly desirable, the real- ization of such requires a strong base of mixed technol- ogy. A new addition to the NVM family is the flash EEPROM. With its small cell size as the OTP EPROM and its electrical erasability as the full-featured EEPROM, flash EEPROM becomes the best compromise for den- sity and flexibility. However, for low-cost user- programmable applications, OTP EPROM is still the choice. It is the purpose of this article to describe the idea of achieving the OTP EPROM cost/bit perform- ance by building it with a one-transistor (1T) flash EEPROM core in a mixed technology environment.