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A SIMPLIFIED REFRACTORY GATE PROCESS FOR HIGH PERFORMANCE GaAs RF FETs

IP.com Disclosure Number: IPCOM000006718D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-25

Publishing Venue

Motorola

Related People

Authors:
Vernon R O'Neil George B. Norris Vijay Nair Charles E. Weitzel Saeid N. Tehrani

Abstract

The Authors have devised an improved process for As one can see above, the critical gate dimension is production of refractory gate GaAs FETs intended for set by the amount of undercut of the gate etch. This can RF applications. This process will make production sim- be diflicult to control to better than 0.1 micron because pler and reduce the variation in RF parameters of the the metal etch tends to be somewhat isotropic. Also, finished devices. In order to show the advantages of this one would like to make contact to the top of the gate process, below we will first describe the present with a low resistance metal layer such as aluminum, ("MAFET") process as used at Motorola then we will and this can require a very tine via opening involving describe the improved ("I&WET II") process and dis- tricky processing because the gate may be 0.5 micron cuss the advantages this new process achieves. or less in width.