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A NEW DESIGN OF SINGLE WAFER DRY PLASMA ETCHERS WITH DEFECTIVITY REDUCTION CAPABILITY

IP.com Disclosure Number: IPCOM000006722D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-25
Document File: 1 page(s) / 62K

Publishing Venue

Motorola

Related People

Authors:
John McDonald Ping Wang Doug Welter Robert Woodburn

Abstract

As the geometries of VLSI devices continue to shrink, not only do the etch processes become more challenging, but the contamination reduction/control issues become more critical. A typical etch process mod- ule will use several separate steps to form the pattern image as well as clean the various residues and particles from the wafer (megasonic cleans and veil removal processes). Numerous types of associated equipment (both wet and dry chemistry) are used for this purpose. These multiple process steps typically require extensive wafer handling, long cycle times, large floor space, and additional direct labor for operation.