Browse Prior Art Database

SELECTIVE SUBSTRATE CONTACT WITH DUAL WIDTH TRENCHES

IP.com Disclosure Number: IPCOM000006735D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-28

Publishing Venue

Motorola

Related People

Authors:
James J. Wang

Abstract

For high speed bipolar and BiCMOS transistors, parasitic capacitances must be minimized. Base and col- lector side-walls add sign&ant capacitance to substrate. Reducing side-wall capacitances therefore improve tran- sistor speed and performance. In addition, new chip pack- ages require die front side contact to substrate. Trench technology can provide isolation between transistors, cre- ate minimal side-wall capacitances, and allow electrical contact top- substrate from the die front surface.