DENSE PACKAGING FOR HIGH SPEED CACHE MEMORY (FAST STATIC RAM) AND MAIN MEMORY (DRAM)
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-28
In computer operation, a high speed intermediate cache memory enhances computation throughput. For example, on a RISC processor with a small on-chip pri- mary cache, a larger second level off-chip cache may be used. Cache memories may be used similarly with CISC processors. Instructions and data must flow to and from the FSRAM cache chips. For highest system through- put, the instruction and data interchange must occur in minimum access time for read and write. The goal is to bring to the processor the immanently needed instruc- tions and data contained in the off-chip cache with mini- mum package/interconnect related delay. As processors become faster packaging delays in cache access will pro- duce an increasing percentage of access delay. When data and instructions needed by the processor are not present when needed, the processor must wait. Address and data signals to and from each of the FSRAMs, pass through the packaging and interconnect The delay prob- lem is greater for off-chip drivers implemented in CMOS. Full receiver switching occurs only tier the signal reflects back from the end of the line (at the last memory in a daisy chain connection). By miniaturizing the memory packages, the round-trip board path can be significantly reduced.