Browse Prior Art Database

CONTROLLED SLEW RATE OUTPUT PAD

IP.com Disclosure Number: IPCOM000006740D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-28
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

Authors:
Philip McEntarfer Jeffrey Porter

Abstract

A classical problem in integrated circuit design is controlling the slew rate of digital output signals. Signals that are too slow result in low operation speeds and signals which are too fast result in such effects as EMI noise and ringing of signals due to transmission line effects. Typical CMOS processes result in uncontrolled edge rate variations of four or five to one over normal temperature, voltage, and process variation. Combine this with the addition of capacitive load variation and the problem is even more ditlicult. The described cir- cuits sense the output voltage and provide a feedback signal to control the output edge rate. Edge rate com- pensation is provided for varying capacitive loads as well as reducing process, temperature, and voltage sensitivity.