Browse Prior Art Database

JTAG CLOCK & CONTROL SIGNAL DISTRIBUTION SCHEME

IP.com Disclosure Number: IPCOM000006746D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-29

Publishing Venue

Motorola

Related People

Authors:
Timothy R. Jones

Abstract

This invention applies to integrated circuits which make use of boundary scan architecture. For informa- tion on JTAG boundary scan refer to the document enti- tled "IEEE Standard Test Access Port and Boundary- Scan Architecture, IEEE Std. 1149.1-9990" In typical sea-of-gates macrocell/gate arrays the cir- cuit is created solely by customizing the metal intercon- nect of these gates. Motorola's H4C family of CMOS arrays are a cross behveen gate arrays and standard cells in that they are sea-of-gates arrays which have the added capability of accommodating fully-diffused "big blocks: such as RAM's and MPU's. In Figures 1-3 a dotted lie marks the boundary between the core and periphery of an H4C array. The core consists of the sea-of-gates and big blocks. The periphery consists of I/O cells, or sites, which are typically configured as input, output or bidi- rectional buffers in order to interface the core logic to circuitry external to the array. When JTAG boundary scan methodology is used on an H4C array, I/O cells which are pinned-out are configured as Boundary Scan Cells (BSC's), which include some logic in addition to the aforementioned chip interface butlers. Figure 4 shows the logic. and I/O buffer portions of a bidirectional BSC, and the associated JTAG clock and control signals. This invention consists of a unique scheme for distributing these signals from their respective sources in the array core to all BSC's around the periphery ofthe chip.