Browse Prior Art Database

GATE-OVERLAPPED ELEVATED SOURCE/DRAIN MOSFET

IP.com Disclosure Number: IPCOM000006747D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-29

Publishing Venue

Motorola

Related People

Authors:
James R. Pfiester Carlos Mazure James D. Hayden Howard C. Kirsch

Abstract

Lightly-doped drain (LDD) structures are typically used to suppress hot-carrier effects in submicron CMOS devices [ 11. The conventional LDD spacer process con- sists of a low-dose source/drain implantation performed after polysilicon gate etch which is followed by the dep- osition and reactive-ion etch of a dielectric material to form a sidewall spacer offset for a subsequent high-dose source/drain implantation. The reduction in the lateral electric field results in lower substrate currents-and longer hot-carrier lifetimes. Optimization of the LDD struc- ture typicalIy requires higher LDD implantation doses than that which would correspond to minimum sub- strate current generation [2]. This is due to modulation of the series resistance caused by hot-carrier induced trapped charge over the LDD region. Since this LDD region resides outside the polysilicon gate, the trapped charge can push the current flow below the surface and degrade the gain of the device.