Browse Prior Art Database

A LOW COST BUMPED THERMAL TEST CHIP ASSEMBLY

IP.com Disclosure Number: IPCOM000006755D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-30
Document File: 3 page(s) / 204K

Publishing Venue

Motorola

Related People

Authors:
Tien-Yu Tom Lee

Abstract

DESCRIPTION OF THE CONCEPT The side view of the bumped thermal test chip assem- bly is shown in Figure I. It is proposed to die bond an existing thermal test chip on the top side of an FR-4 board. The die bond material is a high-thermal- conductivity epoxy (for example: silver-filled epoxy). The I/OS from the test chip are connected to the board by wire-bonding. Most test chips have metal pads for wire bond. For a TAB version of test chip, wire-bond interconnections can apply to copper bumps (or gold bumps) which were positioned peripherally. In case of a flip-chip version of a test chip, which has solder bumps (PblSn) positioned peripherally, a wire-bonder using sol- der wire can connect these solder bumps to the board. In summary, an existing thermal test chip can be bonded to the board directly; its I/OS can be connected to the board by wires; no extra process is required prior to wire bonding.