LOGIC CIRCUIT FOR SELECTING JUNCTION TEMPERATURES FOR ASIC CMOS RELIABILITY AND YIELD ENHANCEMENT
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-31
This discussion deals with an enhancement to a design methodology entitled 'Logic Circuit for ASIC Reliability and Yield Enhancement' (patent pending- docket no. SCO6873C) which provides control over the junction temperature of CMOS ASIC's, regardless of packaging technology. The general purpose behind the design methodology remains the same-to support the burn-in environment associated with device/package qualifications and to facilitate ongoing yield enhancement efforts. The circuit enhancement deals with the issue that certain packaging technologies associated with today's CMOS gate arrays, such as TAB, cannot be put into an oven to set the desired junction temperature. This dilemma is complicated by one of the main advantages of CMOS-low power. Circuit operation will be discussed by first describing the initial circuit followed by that which includes the enhancement.