Browse Prior Art Database

A MULTI-STAGE SIGMA-DELTA CONVERTER ARCHITECTURE UTILIZING MULTIPLE SINGLE BIT OUTPUTS

IP.com Disclosure Number: IPCOM000006828D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2002-Feb-06
Document File: 2 page(s) / 130K

Publishing Venue

Motorola

Related People

Authors:
Robert C. Ledzius

Abstract

This paper presents a method for utilizing multiple output single bit stages to achieve a multi-bit sigma delta output that reduces output quantiaation noise without the matching requirements of a conventional multibit quantizer. Although the example is shown using a clas- sical 2nd order sigma delta modulator, the principle can also be applied to higher order modulators as well. The architecture is applicable to both Analog-to-Digital Converters @DC's) as well as Digital-to-Analog Con- verters (DAC's).