Browse Prior Art Database

ANISO-/ISO-/ANISOTROPIC VIA PROCESS FOR SUBMICRON DEVICE METAL INTERCONNECT

IP.com Disclosure Number: IPCOM000006976D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2002-Feb-13
Document File: 2 page(s) / 71K

Publishing Venue

Motorola

Related People

Authors:
Ping Wang

Abstract

In VLSI device metal interconnect, the metal step coverage strongly depends on the sidewall slope and aspect ratio of the via. As device feature sizes are scaling down to micron regime, the aspect ratios become larger, it is important and challenging to obtain a good metal step coverage at the via holes.