Browse Prior Art Database

DYNAMIC PRIORITIZATION OF LOADS AND STORES FOR HIGH PERFORMANCE RISC ENGINES

IP.com Disclosure Number: IPCOM000006986D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-14
Document File: 3 page(s) / 201K

Publishing Venue

Motorola

Related People

Authors:
Kara Basden Pepe Bill Moyer

Abstract

Buffering memory accesses from issue time to cache/memory access time is a feature which high performance microprocessor implementations are starting to include. The buffers effectively decouple instruction issue from cache/memory availability. Per- formance is improved since fewer instances of instruc- tion issue stalling occur. The addition of memory access buffers may require the microarchitecture to use a prioritization algorithm to choose the order the buffered accesses are executed.