Browse Prior Art Database

SELF-VERIFYING DESIGN RELEASE PROCESS

IP.com Disclosure Number: IPCOM000007031D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-19
Document File: 2 page(s) / 104K

Publishing Venue

Motorola

Related People

Authors:
Michael Stanley

Abstract

ASIC design kits typically contain copies of Motorola databases and are installed on-site at cus- tomer locations. Motorola customers complete ASIC designs using these kits and then send them to Motorola for production. Inaccuracies in the release process can result from: . incomplete data * differences that may develop between the "mas- ter" databases at Motorola and copies used by the customer during development of their design. * differences in production software introduced by routine software maintenance This paper discusses one technique used to reduce errors resulting From the above. This method was implemented as part ofthe IOGEN program; which is a sofiware tool for generation of custom I/O cells based upon user specified parameters. These include: . I/O type: Input, Output, Bidirectional or spe- cial scan control cells . External logic level * Internal logic level * Use ofJTAG control logic * Choice of input termination * Logic choices: inverting vs. non-inverting buff- ers, tristate buffers, differential logic, etc. * Input and output drive levels * Output slew rate control * Physical structure for multi-site I/O Parameter options are specitied via cyclic fields (The user makes a selection by clicking on the field and choosing from a pop-up menu). I/O cells are constructed out of lower level primitives in a build- ing block approach, based upon cell templates that are selected based upon these parameters. The tem- plates specie what types of cells should be used for lower level instances and how they should be interconnected. IOGEN generates a symbol, sche- matic, and other database entries required during 0 Motorola. inc. 1993 logical design of the ASIC.