DIGITAL CLOCK PRESCALER
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-20
The described invention provides an efficient and versatile method of obtaining a desired clock rate from an arbitrary system clock. The method is completely synchronous, uses very little hardware, is extremely low power, and is very manufacturable and reliable. The structure is optimized for ASIC implementation, and can further be made program- mable to accommodate different systems. It is a direct and simple replacement for a complex phase locked loop, which would require many gates if implemented digitally, or several external components to imple- ment in analog circuitry.