Browse Prior Art Database

GATE CHAIN/RING TEST METHOD FOR SILICON AREA REDUCTION

IP.com Disclosure Number: IPCOM000007065D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-22
Document File: 1 page(s) / 66K

Publishing Venue

Motorola

Related People

Authors:
Jim Caravella David Mietus

Abstract

Existing methods used for measuring the aver- mize the errors associated with the actual measure- age propagation delays of gate chains/rings often ment. In a gate chain, this can be illustrated using require a large number of stages in order to mini- the following equation: - fT T ' - 'chain error '*, stage = x= 7 'chain + & N where T 'chain = measured delay = delay of chain = delay associated with error sources Tp, stage = delay per stage N = number of stages As shown by the equation, the measurement error can be minimized by incorporating enough stages in the chain, i.e. by N being large. The error sources can include off-chip buffering, MUX stages, enabling NAND gates, and mismatches in stage load- ing. The typical means of measuring gate chains is to determine the phase delay between the input and output waveforms, while the measurement for a ring is the hequency ofoscillation ofthe output waveform. In both cases, the measurement includes the contri- bution of the aforementioned error sources. If the number of stages used in the gate chain/ring could be reduced via minimization of the error sources contributions, this effectively would reduce the sili- con area used in the fabrication of the gate chains/rings.