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REDUCED CAPACITANCE AND BASE-RESISTANCE NPN FOR CMOS-BASED BiCMOS

IP.com Disclosure Number: IPCOM000007067D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-22

Publishing Venue

Motorola

Related People

Authors:
Robert H. Reuss

Abstract

A modification to a CMOS-based BiCMOS proc- ess is described. With a modest increase in process complexity, a higher performance bipolar device mod- ule can be retrofitted into the baseline without per- turbation of the CMOS parameters. This allows an advanced NPN device to be incorporated into existing CMOS or BiCMOS designs to achieve improved per- formance without the need to shrink design rules. The bipolar module is placed aher the CMOS mod- ule because RTA is performed as the last high- temperature operation to maximize device perform- ance. Insertion of the bipolar module prior to the CMOS would result in dopant precipitation and poor electrical characteristics because furnace operations must be kept at c 900°C in advanced CMOS processes.