OPTIMAL 64-BIT SINGLE-ERROR CORRECTION/DOUBLE-ERROR DETECTION CIRCUIT
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2002-Feb-25
This publication describes a circuit for correcting single-bit errors, detecting both single- and double- bit errors, and generating corresponding checkbits. The circuit can operate as encoder or decoder. As an encoder, based on a 64-bit input data word, a corresponding 8-bit checkword is generated. As a decoder, two modes are possible: detection and cor- rection. In detection mode, all single-, all double-, and some multiple-bit errors can be detected in the 72-bit input code word comprising a 64-bit data word and an 8-bit checkword. In correction mode, single- bit errors in the input code word can be corrected. A block diagram is shown in Figure 1.