Browse Prior Art Database

VERY HIGH SPEED DELAY LINE

IP.com Disclosure Number: IPCOM000007107D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2002-Feb-26

Publishing Venue

Motorola

Related People

Authors:
Amir Haim Tehuda Shvager

Abstract

To test Very Large Scale Integration (VLSI) sem- iconductor devices, clock signals generated by a clock generator are 'tuned' to the operating clock hequency of the VLSI device, so that they can be fed into the inputs of the device to generate meaningful output signals from the device outputs.