VERY HIGH SPEED DELAY LINE

Publishing Venue

Motorola

Related People

Abstract

To test Very Large Scale Integration (VLSI) sem- iconductor devices, clock signals generated by a clock generator are 'tuned' to the operating clock hequency of the VLSI device, so that they can be fed into the inputs of the device to generate meaningful output signals from the device outputs.

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Technical Developments Volume 21 February 1994

VERY. HIGH SPEED DELAY LINE

XORed to generate a signal E which is a clock sig- nal having the same frequency as the input clock, but is delayed by the amount set by the delay lines.

  Logic gates in the circuit generate hazards, which lead to inherent instabilities in the system, such that the delayed clock signal F may not have a stable delay time. Therefore, two non-delayed half frequency clock signals I and J are XORed to generate a fur- ther clock signal K, having the original input clock frequency. The clock signal K is used as a reference clock instead of the original input clock signal A. In this way logic hazards are avoided.

  The arrangement enables the implementation of clock delays for frequencies up to twice the value of the maximum delay line operating frequency. Two arrangements could be used in parallel contigura- tion to increase this to four times the maximum delay line frequency, and so on.

  Using 45MHz delay lines, it is therefore possi- ble to implement 90 and 180MHz delay line arrange- ments as described above, allowing VLSI devices to be tested.

by Amir Haim and Tehuda Shvager

  To test Very Large Scale Integration (VLSI) sem- iconductor devices, clock signals generated by a clock generator are 'tuned' to the operating clock hequency of the VLSI device, so that they can be fed into the inputs of the device to generate meaningful output signals from the device outputs.

  The 'tuning' of the clo...