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VERY HIGH SPEED DELAY LINE Disclosure Number: IPCOM000007107D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2002-Feb-26

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Amir Haim Tehuda Shvager


To test Very Large Scale Integration (VLSI) sem- iconductor devices, clock signals generated by a clock generator are 'tuned' to the operating clock hequency of the VLSI device, so that they can be fed into the inputs of the device to generate meaningful output signals from the device outputs.