Browse Prior Art Database

SERIALIZING HIERARCHICAL FORMATTING TOOL (SHiFT) FOR SERIALIZING PARALLEL TEST PATTERNS IN A PARTITIONED CHIP ARCHITECTURE

IP.com Disclosure Number: IPCOM000007130D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2002-Feb-27
Document File: 2 page(s) / 127K

Publishing Venue

Motorola

Related People

Authors:
Steven E. Cozart Richard L. Greene

Abstract

Partitioned chips present several problems related ,to testing. It is desirable to: 1) Provide a methodical flow from design to pat- tern formatting to simulation verification and final test patterns. Convert parallel test patterns (gener- ated by ATPG or any other method) to serialized vectors for testing the design, 2) Provide the ability to serialize ATPG gener- ated patterns for an embedded block in a chip. This would allow the block designer to verify that the vectors will be correctly serialized for their block. Furthermore, this feature could allow great flexibil- ity in partitioning ATPG in a complex chip by NOT requiring boundary scan elements.