Publishing Venue
The IP.com Prior Art Database
Abstract
Disclosed is a method for a high-density small form factor (SFF) connector for a gigabit transceiver. Benefits include an improved connector at data rates greater than 10 Gb/s.
Method for a high-density SSF connector for a gigabit
transceiver
Disclosed is a method for a high-density small form factor (SFF)
connector for a gigabit transceiver. Benefits include an improved connector at
data rates greater than 10 Gb/s.
Description
The
disclosed method connects a transceiver to a motherboard. The components of the
method include:
• Dual
staggered pad row pattern on the top and bottom of a transceiver substrate
• Female receptacle with
mating pins to connect the transceiver substrate to the motherboard
The
disclosed method maintains a 50-ohm signal impedance from transceiver to
motherboard at frequencies greater than 10 Gb/s. The 50-ohm impedance is
maintained by addressing the following issues:
• Minimizing
the inductive loops created by the TxRx contact pins in the female receptacle
• Minimizing the changes
in capacitance by the movement of the TxRx contact pins in the female
receptacle
These
issues are addressed by:
• Layout
of ground and signal lines through the female receptacle
• Control of the TxRx
contact pin to ground plane displacement when the TxRx substrate is plugged in
See
Figure 1 for a cross-section view of the TxRx substrate and motherboard-to-TxRx
female receptacle. See Figure 2 for a 3-D view of the TxRx connector. See
Figure 3 for a top view of the TxRx connector.
Advantages
The
disclosed method enables high pin count, pluggable small form factor (SFF)
transceivers to connect to motherboards at data rates greater than 10 Gb/s.
Fig. 1...