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INTERNAL TERMINATION OF CPU SPACE CYCLES IN REDUCED PINCOUNT MCUs

IP.com Disclosure Number: IPCOM000007154D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2002-Feb-28
Document File: 1 page(s) / 79K

Publishing Venue

Motorola

Related People

Authors:
Oded Yishay Ann Harwood Joe Jelemensky

Abstract

In the Motorola Modular Microcontroller Fam- ily, as in the 68000 family, the hmction code signals FC[2:0] are basically an extension of the address bus, providing multiple address spaces. These spaces are designated as either user or supervisor, and program or data spaces. One address space has been desig- nated as CPU space to allow the processor to acquire specific control information not normally associated with read or write bus cycles. CPU space cycles are indicated when all FC[2:0] are asserted (logical 1).