A MECHANISM TO OUTPUT INTERNAL STATE INFORMATION DURING IDLE BUS CYCLES
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-01
One of the most serious problems facing users of complex microprocessors (MPU) during system debug is the relative inability to determine what is happening within the device. As on-chip caches become larger and larger, the corresponding num- ber of external bus cycles needed to reference instruc- tions and operands is typically reduced. This factor coupled with the increased complexity caused by the implementation of sophisticated microarchitec- tures makes system-level debug and performance analysis difficult. The use of in-circuit emulators may provide relief to some users, but in many cases, the use of this technology may require the MPU to be configured in a manner that a failure completely disappears or real-time performance analysis is impossible.