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OPTIMAL 32-BIT SINGLE-ERROR CORRECTION/DOUBLE-ERROR DETECTION CIRCUIT

IP.com Disclosure Number: IPCOM000007220D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-06

Publishing Venue

Motorola

Related People

Authors:
Scott E. Lloyd

Abstract

This publication describes a circuit for correcting single-bit errors, detecting both single- and double- bit errors, and generating corresponding checkbits. The circuit can operate as encoder or decoder. As an encoder, based on a 32-bit input data word, a corresponding 7-bit checkword is generated. As a decoder, two modes are possible: detection and cor- rection. In detection mode, all single-, a11 double-, and some triple-bit errors can be detected in the 39-bit input code word comprising a 32-bit data word and an 7-bit checkword. In correction mode, single- bit errors in the input code word can be corrected. A block diagram is shown in Figure 1.