A CMOS GATE CAPACITOR WITH ENHANCED PELIABILITY FOR OPTIMAL PERFORMANCE AND AREA UTILIZATION
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-06
Power supply noise is a significant problem in large, synchronous, CMOS integrated circuits (e.g., microprocessors). First, noise affects the noise mar- gin of the circuits and, therefore, affects the fimc- tionally of the device (adversely impacting yields). Second, overall power-supply noise contracts and expands since VDD and VSS noise are generally sinusoidal but 180" out of phase with respect to each other. Simulations show that for each 1OOmV of power-supply collapse, there is approximately a 3% reduction in device speed. The frequency of supply noise is dictated by the package inductance and the overall chip capacitance (f = 1/(2rrsqrt(LC))), so it need not be in phase with the chip clocks and can affect any critical speed path. Power-supply collapse also adversely impacts yield and performance.