PREVENTING FALSE LATCHING IN VLSI CIRCUITS
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-07
A very common problem in modern VLSI cir- cuits is false latching due to glitches in the enable signal arising out of violation of the setup time. An Ideal enable signal has a setup and hold time rela- tive to the latching clock. Violations of this setup and hold time can result due to the following reasons: 1. An oversight in design which did not account for any number of boundary conditions which cause the enable signal timing requirements to be vio- lated. For instance loading due long metal lines.