LOW POWER, LOW COMPLEXITY LEVEL SENSITIVE SCAN LATCH IN CMOS TECHNOLOGY
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2002-Mar-12
CIRCUIT DESCRIPTION This publication introduces a new Level Sensi- tive Scan Latch (LSSL) with reduced power and low gate count. The most important advantages are that the gate count is reduced by -30% and the power consumption is reduced by -80% (toggling clock only) by -50% (toggling clock and data) compared to current designs (see [l]). The reduction is larger in macros containing multiple LSSLs because there will be only one clock driver set.