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MICROCODE-CONTROLLED PRECHARGE SIGNAL INHIBIT FOR LOW POWER EXECUTION UNIT BUSES

IP.com Disclosure Number: IPCOM000007383D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2002-Mar-20
Document File: 3 page(s) / 87K

Publishing Venue

Motorola

Related People

Authors:
Greg Viot Claire Schlosser Robert Amedeo

Abstract

On existing microcoded CPUs, microcycles are execution unit buses can be driven by registers, as divided into 4 time periods, referred to as Tl, T2, specified by the microinstruction for the microcycle; T3, and T4. Periods T2 and T4 are reserved for see Figure 1. Field encodings within a microinstruc- precharging the buses within the Execution Unit of tion specify which registers access which buses; see the CPU, and no register is permitted to access the Figure 2. buses during these periods. During Tl and T3, the Figure 1. Microcycle divided into 4 time periods one microcycle : T3 T4 Tl T2 T3 T4 Tl T2 T3 T2,T4 = buses being precharged Tl ,T3 = buses being accessed A unique encoding is usually used to specify a bus during Tl, the field encoding that specifies when no registers are driving a bus; see Figure 3. this can also be used to inhibit precharging of that This particular encoding can trigger a signal to the bus that would normally occur during the following precharge logic to inhibit the generation of the T2. Similarly, if a bus is not driven during T3, then precharge signal, thereby sustaining the present the precharge signal normally generated during T4 precharge state until the next active period is detected; can be inhibited. see Figures 4 and 5. For example, if no register drives 0 Motorola. 1°C. 19% 99 MOTOROLA Technical Developments Volume 24 March 1995 Figure 2. Field within microinstruction decoded to select a register microinstruction I n/ / - reg 1 bus ----I> reg 2 driver - reg 3 D select : logic , - reg2"-1 Figure 3. Sample encodings for a 3-bit field field register selected mlue to drive bus ooo no driver 001 reg 1 010 reg 2 011 reg 3 100 reg 4 101 reg 5 110 reg 6 111 reg 7 100 0 Motorola. 1°C. 1995 MO-LA Technical Developments Volume 24 March 1995 @ Figure 4. Field decoded to select a register (w/precharge inhibit) microinstruction n ---E reg 1 bus reg 2 driver reg 3 select ' 0 logic , L reg 21 cr> precharie inhibit Figure 5. Sample encodings for a 3-bit field (w/precharge inhibit) field register selected value to drive bus 000 no driver @recharge inhibit) 001 reg 1 010 reg 2 011 reg 3 100 reg 4 101 reg 5 110 reg 6 111 reg 7 0 Motorola. 1°C. 1995 101