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Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2002-Mar-28

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John R. Melton Mak So


The circuit described below determines the clock frequency required for the switched capacitor filter based upon the latch rate to the DACs assuming 2X oversampling, the sample rate could be 4X or 8X etc. if desired. In this case the additional logic auto- matically adjusts the corner freq. of the SCF as the sample rate is changed from one modulation for- mat to another. Suppose a particular modulation for- mat required a baseband bandwidth of 4 kHz on each of the I & Q channels and the standard sam- pling rate chosen was 2X, the latch rate would be 16 kHz. The clock would always be fixed at say 4.8 MHz. The SCF Clk circuit is designed such that it generates a clock for the SCF that is 50 times the desired corner Frequency, see Maxim SCF MAX297. The SCF Clk generator circuit accepts the latch sig- nal as an input and assumes 2X over sampling and can subsequently uniquely generate or select from a predetermined set offrequencies the proper SCF clock and output it to the filters. To reconfigure the cir- cuit for a new baseband requirement that corresponds to a wider or narrower bandwidth one simply changes the latch rate following the 2X or 4X oversampling rule that the SCF Clk generator circuit was designed around. With the I/Q upconverter following the var- iable reconstruction filter system, nearly any modu- lation scheme and BW can be implemented in a DSP and the hardware readily adapts to accept it with no physical change to the board. Alternatively, the system could also be programmable via a host with some additional logic.