ANALOG HARDWARE BUILT-IN SELF TEST ARCHITECTURE
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2002-Apr-04
Increasing product complexities and shrinking product sizes drives higher functional and device inte- gration levels. Increased integration has many advan- tages, but also has the disadvantage of reduced testability due to reduced observability and control- lability of internal nodes. In addition, customers expect the products to be more and more capable of detecting and diagnosing problems by itself, Existing fault detection and diagnosic methods are currently limited to "off-line" testing, where a known stimulus is applied to the circuit-under-test, and the circuit response is monitored and compared to the expected values. Furthermore, a thorough test of the hardware-particularly analog hardware-is usually only possible in a dedicated test fixture, such as the manufacturing front-end board-level test area. DESCRIPTION OF THE INVENTION: The invention provides a two-phased method of assessing the analog hardware "health" using non- traditional built-in selftest (BIST) techniques.