STACKED CAPACITOR FORMED BY POLY SPACER PROCESS
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2002-Apr-04
As the SRAM bitcell area is continually being reduced to meet the demands of higher density requirements, the ability to store enough charge for soft error protection becomes more difficult. This is especially critical for TFT-based bitcells due to their small cell size and the inability of the tfl load to respond quickly to soft-error interruptions [l]. Although stack capacitors can be used to provide additional capacitance for over-gated ttl-based SRAM bitcells [2J, integration of the stacked capacitor into an undergated m-based bitcell  is difhcult since the highest capacitance is formed between the tfl gate poly and an additional poly plate. In an under- gated tfi bitcell, the tl? gate poly is underneath the tll channel poly layer which significantly reduces the surface area for capacitance with another polysilicon layer positioned above the tit channel poly. Similarly, forming a capacitance between the ttl gate poly and an underlying polysilicon layer (such as the window poly layer used for Vss interconnection in the bitcell array) is difficult since a thin dielectric separation would most likely result in shorting of the tl? chan- nel poly to window poly due to the HF-preclean prior to tft channel poly depositon.