FLIP CHIP CARRIER WITH ADJUSTABLE GROUND LEAD INDUCTANCE
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2002-Apr-10
This is a description of how the series intercon- nection of plated through holes in a substrate can be used to provide RF stability for a transistor when it is packaged in a flip chip configuration. RF power transistor stability for common source and common emitter configurations is affected by the inductance ofthe respective source and emitter interconnections. In a wire bonded package the optimum inductance is tuned by means of the number, length and diam- eter of the wire bonds used. In a flip chip package, the low inductance of bump interconnections can cause the same transistor to become unstable com- pared to when it is wire bonded.