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Browse Prior Art Database

MEMORY ARRAY STATE NODE IDENTIFICATION TOOL

IP.com Disclosure Number: IPCOM000007619D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2002-Apr-10

Publishing Venue

Motorola

Related People

Authors:
Manish Pandey Randal E. Bryant

Abstract

Memory arrays in this document refer to a SBAM or DRAM core with at least one write port. Exam- ples of such arrays include multi-ported register files, cache memory SRAM core and cache tag arrays. Identification of state nodes in a memory array is an important prerequisite for many simulation and for- mal verification tasks. Circuit properties are usually expressed in terms of these nodes. Also, for simula- tion, we can initialize the circuit to a given state by setting the internal state nodes to certain values.